Apparatus and method to set signal compensation settings for a data storage device

ABSTRACT

A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length.

FIELD OF THE INVENTION

This invention relates to an apparatus and method to set signalcompensation settings for a data storage device disposed in aninformation storage and retrieval system.

BACKGROUND OF THE INVENTION

Data storage and retrieval systems are used to store informationprovided by one or more host computer systems. Such data storage andretrieval systems receive requests to write information to one or moredata storage devices, and requests to retrieve information from thoseone or more data storage devices. Upon receipt of a read request, thesystem recalls information from the one or more data storage devices andmoves that information to the data cache. Thus, the system iscontinuously moving information to and from a plurality of data storagedevices, and to and from the data cache.

What is needed is an apparatus and method to enhance communication ofdata to and from a data storage device disposed in an informationstorage and retrieval system. Applicants' invention provides a method toset signal compensation settings for a data storage device.

SUMMARY OF THE INVENTION

Applicants' invention comprises a method to set signal compensationsettings for a data storage device comprising a first port and a secondport, where that first port is interconnected to a first switch via afirst communication pathway having a predetermined first length. Themethod determines first signal compensation settings based upon thefirst length.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from a reading of the followingdetailed description taken in conjunction with the drawings in whichlike reference designators are used to designate like elements, and inwhich:

FIG. 1 is a block diagram showing a one embodiment of Applicants' datastorage and retrieval system;

FIG. 2 is a block diagram showing the data storage and retrieval systemof FIG. 1 comprising three storage arrays;

FIG. 3 is a block diagram showing one storage array interconnected totwo controllers;

FIG. 4 is a block diagram showing a first communication pathwayinterconnecting a data storage device to a first switch and a secondcommunication pathway interconnecting that data storage device to asecond switch;

FIG. 5 is a flow chart summarizing certain additional steps inApplicants' method;

FIG. 6 is a flow chart summarizing the certain steps of Applicants'method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This invention is described in preferred embodiments in the followingdescription with reference to the Figures, in which like numbersrepresent the same or similar elements. The invention will be describedas embodied in an information storage and retrieval system whichincludes a plurality of device adapters, and a data cache. The followingdescription of Applicant's method is not meant, however, to limitApplicant's invention to data processing applications, as the inventionherein can be generally applied to providing data to and frominformation storage devices.

Referring now to FIG. 1, information storage and retrieval system 100 iscapable of communication with host computer 390 via communication link395. The illustrated embodiment of FIG. 1 shows a single host computer.In other embodiments, Applicants' information storage and retrievalsystem is capable of communicating with a plurality of host computers.

Host computer 390 comprises a computer system, such as a mainframe,personal computer, workstation, and combinations thereof, including anoperating system such as Windows, AIX, Unix, MVS, LINUX, etc. (Windowsis a registered trademark of Microsoft Corporation; AIX is a registeredtrademark and MVS is a trademark of IBM Corporation; UNIX is aregistered trademark in the United States and other countries licensedexclusively through The Open Group; and LINUX is a registered trademarkof Linus Torvald).) In certain embodiments, host computer 390 furtherincludes a storage management program. The storage management program inthe host computer 390 may include the functionality of storagemanagement type programs known in the art that manage the transfer ofdata to and from a data storage and retrieval system, such as the IBMDFSMS implemented in the IBM MVS operating system.

In certain embodiments, Applicants' information storage and retrievalsystem includes a plurality of host adapters. In the illustratedembodiment of FIG. 1, system 100 comprises host adapters 102-105,107-110, 112-115 and 117-120. In other embodiments, Applicants'information storage and retrieval system includes fewer than 16 hostadapters. Regardless of the number of host adapters disposed in anyembodiments of Applicants' system, each of those host adapters comprisesa shared resource that has equal access to both central processing/cacheelements 130 and 140.

Each host adapter may comprise one or more Fibre Channel ports, one ormore FICON ports, one or more ESCON ports, or one or more SCSI ports.Each host adapter is connected to both clusters through interconnect bus121 such that each cluster can handle I/O from any host adapter.Internal buses in each subsystem are connected via a Remote I/O bridge155/195 between the processor portions 130/140 and I/O portions 160/170,respectively.

Processor portion 130 includes processor 132 and cache 134. In certainembodiments, processor portion 130 further includes memory 133. Incertain embodiments, memory device 133 comprises random access memory.In certain embodiments, memory device 133 comprises non-volatile memory.

Processor portion 140 includes processor 142 and cache 144. In certainembodiments, processor portion 140 further includes memory 143. Incertain embodiments, memory device 143 comprises random access memory.In certain embodiments, memory device 143 comprises non-volatile memory.

I/O portion 160 comprises a plurality of device adapters 161 which inthe illustrated embodiment of FIG. 1 comprises device adapters 165, 166,167, and 168. I/O portion 160 further comprise nonvolatile storage(“NVS”) 162 and battery backup 164 for NVS 162.

I/O portion 170 comprises a plurality of device adapters 171 which inthe illustrated embodiment of FIG. 1 comprises device adapters 175, 176,177, and 178. I/O portion 170 further comprises nonvolatile storage(“NVS”) 172 and battery backup 174 for NVS 172.

In certain embodiments of Applicants' system, one or more host adapters,processor portion 130, and one or more device adapters are disposed on afirst control card disposed in Applicants' information storage andretrieval system. Similarly, in certain embodiments, one or more hostadapters, processor portion 140, one or more device adapters aredisposed on a second control card disposed in Applicants' informationstorage and retrieval system.

In the illustrated embodiment of FIG. 1, sixteen data storage devicesare organized into two arrays, namely array 180 and array 190. Theillustrated embodiment of FIG. 1 shows two storage device arrays. Eachstorage array appears to a host computer as one or more logical devices.

In certain embodiments, one or more of the data storage devices comprisea plurality of hard disk drive units. In certain embodiments, arrays 180and 190 utilize a RAID protocol. In certain embodiments, arrays 180 and190 comprise what is sometimes called a JBOD array, i.e. “Just a BunchOf Disks” where the array is not configured according to RAID. Incertain embodiments, arrays 180 and 190 comprise what is sometimescalled an SBOD array, i.e. “Switched Bunch Of Disks”.

The illustrated embodiment of FIG. 1 shows two storage device arrays. Inother embodiments, Applicants' system includes a single storage devicearray. In yet other embodiments, Applicants' system includes more thantwo storage device arrays.

In the illustrated embodiment of FIG. 2, Applicants' information storageand retrieval system comprises dual FC-AL loops of switches where thesystem controllers 130 and 140 are interconnected with two FC-AL loops.Each loop contains one or more local controllers, such as localcontrollers 210, 220, 230, 240, 250, and 260.

Each local controller comprises a switch, a processor, and microcode. Incertain embodiments, the switch comprises a Fibre Channel switch. Incertain embodiments, the processor comprises a SES processor. Forexample, local controllers 210, 220, 230, 240, 250, and 260, includeprocessors 212, 222, 232, 242, 252, and 262, respectively. Similarly,local controllers 210, 220, 230, 240, 250, and 260, include switches214, 224, 234, 244, 254, and 264, respectively. In addition, localcontrollers 210, 220, 230, 240, 250, and 260, include microcode 216,226, 236, 246, 256, and 266, respectively.

In certain embodiments, Applicants' apparatus further includes amidplane interconnecting one or more controllers to one or more datastorage devices. In the illustrated embodiment of FIG. 3, controller 210(FIGS. 2, 3) comprises Fibre Channel switch 214 (FIGS. 2, 3, 4) and SESprocessor 212 (FIGS. 2, 3, 4). In the certain embodiments, SES processor212 comprises table 213 wherein table 213 comprises certain defaultsignal compensation settings. A plurality of communication links 320interconnect Fibre Channel switch 216 to midplane 310. A plurality ofcommunication links 340 interconnect data storage devices 270 (FIGS. 2,3, 4) with midplane 310.

Controller 240 (FIGS. 2, 3) comprises Fibre Channel switch 244 (FIGS. 2,3, 4) and SES processor 242 (FIGS. 2, 3, 4). In the certain embodiments,SES processor 242 comprises table 243 wherein table 243 comprisescertain default signal compensation settings. A plurality ofcommunication links 330 interconnect Fibre Channel switch 244 tomidplane 310.

Signals are provided by switch 214 to data storage devices 270 viacommunication links 320, communication links 340, and midplane 310.Similarly, signals are provided by switch 244 to data storage devices270 via communication links 330, communication links 340, and midplane310. Applicants' invention comprises a method to adjust signalcompensation settings based upon the predetermined length of theaggregate communication link between a data storage device and a switch.

Referring now to FIG. 6, in step 610 Applicants' method provides a datastorage device, such as for example data storage device 405 (FIG. 4),where that data storage device comprises a first port, such as port 410(FIG. 4) and a second port, such as port 420 (FIG. 4), interconnectedwith a first switch, such as switch 214 (FIGS. 2, 3, 4) by a firstcommunication pathway, such as communication pathway 430, having a firstlength, where that first length is known. In certain embodiments, step610 further comprises providing a data storage device, such as datastorage device 405, where that data storage device is interconnectedwith a second switch, such as switch 244, by a second communicationpathway 440, having a second length, where that second length is known.

In step 620, Applicants' method provides default signal compensationlevels. In certain embodiments, the default signal compensation levelsof step 620 comprise one or more default input signal compensationsettings. In certain embodiments, the default signal compensation levelsof step 620 comprise one or more default output signal compensationsettings. In certain embodiments, the default signal compensation levelsof step 620 comprise one or more default input signal compensationsettings and one or more default output signal compensation settings.

In certain embodiments, the default signal compensation levels of step620 are established by the manufacturer of the information storage andretrieval system comprising the data storage device. In otherembodiments, the default signal compensation levels are established bythe manufacturer of the data storage device. In yet other embodiments,the default signal compensation levels are set during system startup. Instill other embodiments, the default signal compensation levels areprovided by a host computer.

Applicant's method adjusts certain output signal compensation settingsfor the signals provided by the data storage device to the switch. Incertain embodiments, these output signal compensation settings include,without limitation, signal pre-emphasis, signal amplitude, and outputtermination. As those skilled in the art will appreciate, pre-emphasisincreases the magnitude of certain frequencies with respect to themagnitude of other frequencies, in order to improve the overallsignal-to-noise ratio by minimizing the adverse effects of suchphenomena as attenuation differences in subsequent parts of the system.

Applicants' input signal compensation setting adjusts the sensitivity ofa data storage device to signals provided to that device by a switch. Incertain embodiments, Applicants' input signal compensation settingsinclude, without limitation, signal amplitude, common mode sensitivity,and thresholds for loss of signal.

Referring again to FIG. 6, in step 630 Applicants' method determinesfirst signal compensation settings by adjusting the default signalcompensation levels of step 620 based upon the known first length ofstep 610. In certain embodiments, step 630 is performed by the datastorage device, such as data storage device 405. In other embodiments,step 630 is performed by a processor, such as processor 214,interconnected with the data storage device by the first communicationlink. In certain embodiments, step 630 is performed by an interconnectedhost computer, such as host computer 390 (FIG. 1).

In certain embodiments, Applicants' method transitions from step 620 tostep 510 (FIG. 5). Referring now to FIG. 5, in step 510 Applicants'method encodes the default signal compensation settings in a processor,such as processor 212 (FIGS. 2, 3, 4). In certain embodiments, thosedefault signal compensation settings comprise a table, such as table 213(FIGS. 3, 4), encoded in that processor. In certain embodiments, step510 is performed by the manufacturer of the information storage andretrieval system. In certain embodiments, step 510 is performed atsystem startup.

In step 520, Applicants' method provides power to all or a portion ofApplicants' information storage and retrieval system, where thatnewly-powered portion includes a data storage device. Such a power-onevent may comprise a system startup, a system reset, a power-on restartof the data storage device, and the like.

In certain embodiments, Applicants' method transitions from step 520 tostep 525, wherein the data storage device, such as device 405, queries afirst interconnected processor, such as processor 212, to obtain firstdefault signal compensation settings. In certain embodiments, thosedefault signal compensation settings are encoded in a table, such astable 213, disposed in the processor.

Applicants' method transitions from step 525 to step 535 where incertain embodiments the data storage device sets one or more firstoutput signal compensation settings by adjusting first default signalcompensation settings based upon the predetermined length of a firstcommunication pathway, such as pathway 430, interconnecting the datastorage device and a first switch, such as switch 214. Step 535 furthercomprises setting by the data storage device one or more first inputsignal compensation settings by adjusting first default signalcompensation settings based upon the predetermined length of a firstcommunication pathway, such as pathway 430, interconnecting the datastorage device and a first switch, such as switch 214.

In other embodiments, the data storage device in step 535 sets one ormore first output signal compensation settings by adjusting firstdefault signal compensation settings based upon the address of thatdevice. In these embodiments, each data storage device is assigned anaddress specific to its position in the storage array, such that thelength of the communication pathway for each address is known. Table 1recites addresses for the 16 data storage devices comprising storagearray 270 (FIGS. 2, 3, 4).

TABLE 1 Data Storage Device No. Address 0 0h 1 8h 2 6h 3 Eh 4 7h 5 Fh 61h 7 9h 8 2h 9 Ah 10 3h 11 Bh 12 4h 13 Ch 14 5h 15 DhIn these data storage device address embodiments, step 535 furthercomprises setting by the data storage device one or more first inputsignal compensation settings by adjusting first default signalcompensation settings based upon the data storage device address.

In certain embodiments, Applicants' method transitions from step 535 tostep 550 wherein the data storage device receives signals from a firstinterconnected switch using one or more first input signal compensationsettings, and provides signals to that interconnected first switch usingone or more first output signal compensation settings.

In certain embodiments, Applicants' method transitions from step 535 tostep 545 wherein the data storage device queries a second interconnectedprocessor, such as processor 242, to obtain second default signalcompensation settings. In certain embodiments, those default signalcompensation settings are encoded in a table, such as table 243 (FIG.3), disposed in the processor.

Applicants' method transitions from step 545 to step 555 where incertain embodiments the data storage device sets one or more secondoutput signal compensation settings by adjusting second default signalcompensation settings based upon the predetermined length of a secondcommunication pathway, such as pathway 440, interconnecting the datastorage device and a second switch, such as switch 244. Step 555 furthercomprises setting by the data storage device one or more second inputsignal compensation settings by adjusting second default signalcompensation settings based upon the predetermined length of a secondcommunication pathway, such as pathway 440, interconnecting the datastorage device and a second switch, such as switch 244.

In other embodiments, the data storage device in step 555 sets one ormore second output signal compensation settings by adjusting seconddefault signal compensation settings based upon the address of that datastorage device. In these embodiments, step 555 further comprises settingby the data storage device one or more second input signal compensationsettings by adjusting second default signal compensation settings basedupon the address of the data storage device.

Applicants' method transitions from step 555 to step 580 wherein thedata storage device receives signals from a first interconnected switchusing one or more first input signal compensation settings, and providessignals to that first interconnected switch using one or more firstoutput signal compensation settings, and wherein the data storagedevices receives signals from a second interconnected switch using oneor more second input signal compensation settings, and provides signalsto that second switch using one or more second output signalcompensation settings.

In certain embodiments, Applicants' method transitions from step 520 tostep 530 wherein a first processor, such as processor 212, sets one ormore first output signal compensation settings by adjusting firstdefault signal compensation settings based upon the predetermined lengthof a first communication pathway, such as pathway 430, interconnectingthe data storage device and a first switch, such as switch 214. In theseembodiments, step 530 further comprises setting by the first processorone or more first input signal compensation settings by adjusting firstdefault signal compensation settings based upon the predetermined lengthof a first communication pathway, such as pathway 430, interconnectingthe data storage device and a first switch, such as switch 214.

In other embodiments, in step 530 a first processor, such as processor212, sets one or more first output signal compensation settings byadjusting first default signal compensation settings based upon theaddress of the data storage device. In these embodiments, step 530further comprises setting by the first processor one or more first inputsignal compensation settings by adjusting first default signalcompensation settings based upon the address of the data storage device.Applicants' method transitions from step 530 to step 540 wherein thefirst processor provides the first output signal compensation settingsand the first input signal compensation value to the data storagedevice.

In certain embodiments, Applicants' method transitions from step 540 tostep 550. In other embodiments, Applicants' method transitions from step540 to step 560 wherein a second processor, such as processor 242, setsone or more second output signal compensation settings by adjustingsecond default signal compensation settings based upon the predeterminedlength of a second communication pathway, such as pathway 440,interconnecting the data storage device and a second switch, such asswitch 244. In these embodiments, step 560 further comprises setting bythe second processor one or more second input signal compensationsettings by adjusting second default signal compensation settings basedupon the predetermined length of a second communication pathway, such aspathway 440, interconnecting the data storage device and a secondswitch, such as switch 244.

In other embodiments, in step 560 a second processor, such as processor242, sets one or more second output signal compensation settings byadjusting second default signal compensation settings based upon theaddress of the data storage device. In these embodiments, step 560further comprises setting by the second processor one or more secondinput signal compensation settings by adjusting second default signalcompensation settings based upon the address of the data storage device.

Applicants' method transitions from step 560 to step 570 wherein thesecond processor provides one or more second output signal compensationsettings and one or more second input signal compensation value to thedata storage device. Applicants' method transitions from step 570 tostep 580.

The embodiments of Applicants' method recited in FIGS. 5 and/or 6, maybe implemented separately. Moreover, in certain embodiments, individualsteps recited in FIGS. 5 and/or 6 may be combined, eliminated, orreordered.

In certain embodiments, Applicants' invention includes instructionsresiding in microcode, such as for example microcode 216 (FIG. 2), 226(FIG. 2), 236 (FIG. 2), 246 (FIG. 2), 256 (FIG. 2), and/or 266 (FIG. 2),where those instructions are executed by a processor, such as processor212 (FIG. 2), 222 (FIG. 2), 232 (FIG. 2), 242 (FIG. 2), 252 (FIG. 2),and/or 262 (FIG. 2), respectively, to perform step 630 recited in FIG.6, and/or steps 530, 540, 560, and/or 570, recited in FIG. 5. In certainembodiments, Applicants' invention includes instructions residing in adata storage device, such as data storage device 405 (FIG. 4), toperform step 630 recited in FIG. 6, and/or steps 525, 535, 545, 550,555, and/or 580, recited in FIG. 5.

In other embodiments, Applicants' invention includes instructionsresiding in any other computer program product, where those instructionsare executed by a computer external to, or internal to, system 100, toperform step 630 recited in FIG. 6, and/or steps 530, 540, 560, and/or570, recited in FIG. 5. In either case, the instructions may be encodedin an information storage medium comprising, for example, a magneticinformation storage medium, an optical information storage medium, anelectronic information storage medium, and the like. By “electronicstorage media,” Applicants mean, for example, a device such as a PROM,EPROM, EEPROM, Flash PROM, compactflash, smartmedia, and the like.

While the preferred embodiments of the present invention have beenillustrated in detail, it should be apparent that modifications andadaptations to those embodiments may occur to one skilled in the artwithout departing from the scope of the present invention as set forthin the following claims.

1. A method to set signal compensation settings for a data storagedevice, comprising the steps of: providing a data storage devicecomprising a first port and a second port, wherein said first port isinterconnected to a first switch via a first communication pathwayhaving a predetermined first length; determining first signalcompensation settings based upon said first length; providing defaultsignal compensation settings: wherein said determining step comprisesadjusting said default signal compensation settings based upon saidfirst length; said providing default signal compensation settingsfurther comprises providing one or more default input signalcompensation settings and one or more default output signal compensationsettings; said providing default signal compensation settings stepfurther comprises providing a table comprising said one or more defaultinput signal compensation settings and one or more default output signalcompensation settings; wherein said adjusting step comprises retrievingsaid one or more default input signal compensation settings and one ormore default output signal compensation settings from said table.
 2. Themethod of claim 1, further comprising the step of providing a processorcomprising memory, wherein said processor is capable of communicatingwith said data storage device, further comprising the step of encodingsaid default signal compensation settings in said memory.
 3. The methodof claim 2, further comprising the steps retrieving said default signalcompensation settings by said data storage device from said memory;wherein said determining step further comprises: setting one or morefirst output signal compensation settings by said data storage device;and setting one or more first input signal compensation settings by saiddata storage device.
 4. The method of claim 2, further comprising thesteps retrieving said default signal compensation settings by saidprocessor from said memory; wherein said determining step furthercomprises setting one or more first output signal compensation settingsby said processor, and setting one or more first input signalcompensation settings by said processor; providing to said data storagedevice by said processor said one or more first output signalcompensation settings and said one or more first input signalcompensation settings.